POWER5 Performance Brief
Travis Roy  |  by www.aceshardware.com. All rights reserved. 28.11 | 18:48

64KB /32KB L1 Cache (2-way set assoc. Inst., 4-way set assoc.

Data) 2-way SMT per core, software controlled priority for exec.

Read more on by www.aceshardware.com. All rights reserved.
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